Low voltage CMOS four-quadrant multiplier - Electronics Letters

CMOS technology, and the parasitic capacitances have been extracted from a layout which will be used for the integration of a multilayer perceptron with on-chip learning. The size of a complete 5bit storage cell is 1 2 0 ~ x 69pm ( 1 2 0 ~ x 1 9 ~ for the current sources). The weighted current sources are made, respectively, of 8-, 4-, 2-, I-unit transistors in parallel and 2unit transistors in series for the LSB. This configuration optimises the active-to-total area ratio and consequently the current sources matching. Fig. 3 shows the transient simulation of a 4bit version of this storage cell, with ILsR = 1 nA. The initial state of the cell is B = 1100 (or Bb = OOII), which represents a stored current of 12nA. The input current to the cell before conversion is lI,I = 5.lnA, which must produce the code B = 0101 (or Bb = 1010). This situation shows the four possible bit transitions. The input current I,,, is the drain current of M c . The complete conversion cycle can be described as follows: (3) IMs, = IB, is larger than I,,, and pulls Bb, high (2) the input current to cell 2 is = I,n, and En, is pulled down, which maintains Bb, low. The mirror output transistor M , unsaturates to the value In =4nA; (1) the input current I,,,, of cell l is then I,", I,, = 1.1 nA < I,] = 2nA. The internal node B,, is therefore maintained high; (0) the input current I,.o of cell 0 is then I,", I , = I . I nA > Im = 1 nA. The internal node Bn, falls slowly, pulling Bb,, low. The mirror output transistor M , unsaturates to the value I , + Im = 5nA, which represents the desired quantised stored value.